1. Field of Invention
The present invention relates to a method of manufacturing semiconductor package. More particularly, the present invention relates to a method of manufacturing a ball grid array package with metal peg leads, all connected by trace lines.
2. Description of Related Art
In the semiconductor production industry, the manufacturing of integrated circuits (ICs) is generally divided into three distinct stages. In the first stage, the semiconductor substrates or silicon wafers are formed using an epitaxial technique. In the second stage, various semiconductor devices such as MOS transistors and multi-level interconnects are formed in the semiconductor substrate by various operations. In the third and last stage, the silicon wafers are diced up to form individual dies followed by enclosing the die with suitable material to form a package. The package not only protects the die from mechanical damage, but also provides a medium for electrically connecting the die to other electronic components on a printed circuit board.
In general, an IC module must have a large number of electrical outlets because there are a large number of contacts on a die that needs to be connected. Consequently, hundreds of conductive lines are needed inside the package. In a conventional package, a lead frame is used to connect bonding pads on a die with external contact points outside the package. However, due to the rapid increase in the level of integration for integrated circuits without a corresponding increase in size of the package, the conventional lead frame is simply incapable of providing the necessary number of wiring connections. In addition, electronic products are becoming lighter and smaller all the time due to fierce competition in the marketplace. These market forces provide an impetus for the rapid development of new types of packaging techniques such as chip scale package, chip size package and multi-chip module.
Nowadays, techniques for manufacturing integrated circuits having a line width smaller than 0.18 micron are available. With many breakthroughs in the level of circuit integration, the size of a package has reduced considerably.
A conventional package uses a lead frame as a die carrier with leads protruding from the side of the package. Because these leads are distributed around the periphery of the package, the package must occupy a larger area. Furthermore, the high pin count limits the pitch between leads. In other words, there is a limit to possible package reduction. Consequently, area array package designs are introduced. The contact points of an area array package are usually laid on the bottom surface of the package. Ball grid array (BGA), small outline no-lead (SON) and ball chip carrier (BCC), for example, are all area array packages.
FIGS. 1A through 1E are schematic, cross-sectional views showing the progression of manufacturing steps for fabricating a conventional ball chip carrier package. As shown in FIG. 1A, photoresist material is deposited over surfaces 102a and 102b of a copper substrate 100 to form photoresist layers 104a and 104b, respectively. The photoresist layer 104a is exposed and developed to form ball lead areas 106 that expose a top surface 102a of the copper substrate 100.
As shown in FIG. 1B, a wet etching operation is conducted to etch the copper substrate 100 with the photoresist layers 104a and 104b serving as a mask, thereby forming hemispherical cavities 108 in the ball lead areas 106. An electroplating operation is carried out to form a conformal layer of metallic film 110 over the hemispherical cavities 108.
As shown in FIG. 1C, both photoresist layers 104a and 104b are removed, and a die 112 is attached to the surface 102a. A wire-bonding step is carried out to form metallic wires 114 to link bonding pads (not shown in the figure) on the die 112 with the metallic film 110. The upper surface 102a of the copper substrate 100 is sealed off using plastic material such as resin 116 as shown in FIG. 1D. The resin 116 encloses the die 112, the metallic wires 114 and the metallic film 110 inside the cavity 108.
As shown in FIG. 1E, another wet etching operation is performed to remove the copper substrate 100 (portions labeled 100 in FIG. 1D). Ultimately, the hemispherical metal films 110, the bottom portion of the die 112 and the surface of resin 116 are all exposed to form a complete ball chip carrier package. This type of package utilizes the hemispherical metallic films 110 as leads for connecting with external circuits.
However, the aforementioned package has a potential reliability problem as well as a production yield problem. A metallic film is used to line each lead cavity. Since the metal film is made from precious metal, thickness of the metallic film should be minimized as much as possible. Yet, saving precious metal by forming a thin metallic film makes the film vulnerable to scratches or peelings during transition or transfer. Too much damage to the metallic film may result in bad connections with a printed circuit board and may also lead to reliability problems when the package is finally mounted onto a PCB using surface mount technology (SMT). Consequently, product yield will deteriorate.
Furthermore, as the pin count of each device continues to increase, density of bonding pads on a package board must increase correspondingly. In other words, distance of separation between neighboring bonding pads is shortened. The number of contact points on the package board for connecting with a PCB must correspond to the number of bonding pads on a die. However, the ultimate size and distance of separation of each contact point from its neighbor is restricted by the area available on the package board. Hence, only a contact layout array type is able to accommodate a sufficiently large number of contact points.
Accordingly, the invention provides a method for forming a ball grid array package with trace lines and metal pegs so that the package has a better overall reliability and a higher produce yield. The metal pegs serve as external leads of the package. The metal pegs are arranged to form an array. Molding material is formed only on one side of an internal substrate board, and hence a thinner package is obtained. Furthermore, a bottom surface of the package is exposed for dissipating more heat away from an internal die. In addition, the end surface of each metal peg has an electroplated layer. This electroplated layer confers good bondability, molding characteristics and solderability to the metal pegs so that subsequent soldering processes are easier to conduct. In brief, the package is suitable for housing a high pin count device.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for forming ball grid array package. The ball grid array package has internal trace lines and exposed metal pegs suitable for forming a high pin count device. A metal substrate is provided. Electroplated layers are formed over metal peg regions and a die pad region on the surface of the metal substrate. A layer of substrate material at the top surface of the metal substrate is removed by etching so that thickness of the metal substrate is reduced. Hence, trace lines, die pad and internal metal pegs are formed. A die is attached to the die pad and electrical connections from the die to the internal metal pegs are made. A molding process is carried out to enclose the die, the die pad and the internal metal pegs on one side of the metal substrate using plastic material. The lower surface of the metal substrate is etched to form external metal pegs while exposing the mold material and the bottom surface of the die pad. The internal metal pegs and the external metal pegs are interconnected via the trace lines. A soldering mask layer is formed over the package surface covering the trace lines but exposing the electroplating at the end face of each external metal peg.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.